1. Field of the Invention
The present invention relates generally to non-volatile memory devices, and more particularly, to zero-power electrically erasable and programmable memory cells, such as EEPROM cells.
2. Discussion of the Related Art
Referring to FIG. 1, an example programmable logic device is a programmable AND gate 100 of the prior art. The programmable AND gate 100 includes a first input node 102 for inputting a first input signal, A, and a second input node 104 for inputting a second input signal B. The first input signal, A, is coupled through a first inverter 100 and a second inverter 108 to the gate of a first NMOSFET (N-channel metal oxide semiconductor field effect transistor) 110. The complement of the first input signal, designated as A*, (i.e., the output of the first inverter 106) is coupled to the gate of a second NMOSFET (N-channel metal oxide semiconductor field effect transistor) 112.
Similarly, the second input signal, B, is coupled through a third inverter 114 and a fourth inverter 116 to the gate of a third NMOSFET (N-channel metal oxide semiconductor field effect transistor) 118. The complement of the second input signal, designated as B*, (i.e., the output of the third inverter 114) is coupled to the gate of a fourth NMOSFET (N-channel metal oxide semiconductor field effect transistor) 120.
A first programmable switch 122 is coupled between the drain of the first NMOSFET 110 and an output node 130, and a second programmable switch 124 is coupled between the drain of the second NMOSFET 112 and the output node 130. Similarly, a third programmable switch 126 is coupled between the drain of the third NMOSFET 118 and the output node 130, and a fourth programmable switch 128 is coupled between the drain of the fourth NMOSFET 120 and the output node 130. In addition, a current source 132 is coupled to the output node 130 for charging the output node 130 when the output signal at the output node 130 turns to a logical high state.
For operation of the programmable AND gate 100 of FIG. 1, the first, second, third, and fourth switches 122, 124, 125, and 128 are programmable to be switched open or closed. One of the first and second programmable switches 122 and 124 is programmed to be open, and the other is programmed to be closed. Similarly, one of the third and fourth progammable switches 126 and 128 is programmed to be open, and the other is programmed to be closed.
The output node 130 of the programmable AND gate 100 provides an AND operation (of one of the first input signal, A, or the complement of the first input signal A*, and one of the second input signal, B, or the complement of the second input signal, B*. If the first switch 122 is programmed to be closed with the second switch 124 being programmed to be open, then the programmable AND gate 100 provides an AND operation with the complement of the first input signal, A*, instead of the first input signal, A. On the other hand, if the first switch 122 is programmed to be open with the second switch 124 being programmed to be closed, then the programmable AND gate 100 provides an AND operation with the first input signal, A, instead of the complement of the first input signal, A*.
Similarly, if the third switch 126 is programmed to be closed with the fourth switch 128 being programmed to be open, then the programmable AND gate 100 provides an AND operation with the complement of the second input signal, B*, instead of the second input signal, B. On the other hand, if the third switch 126 is programmed to be open with the fourth switch 128 being programmed to be closed, then the programmable AND gate 100 provides an AND operation with the second input signal, B, instead of the complement of the second input signal, B*.
Thus, in the example illustration of FIG. 1, since the first switch 122 is programmed to be closed while the second switch 124 is programmed to be open, the programmable AND gate 100 provides an AND operation with the complement of the first input signal, A*, instead of the first input signal, A. Also, since the third switch 126 is programmed to be open, while the fourth switch 128 is programmed to be closed, the programmable AND gate 100 provides an AND operation with the second input signal, B, instead of the complement of the second input signal, B*.
Thus, the output node 130 provides an output signal=A*·B. Referring to FIG. 1, only in the case when the first input signal, A, is a logical low state and the second input signal, B, is a logical high state, all of the first, second, third, and fourth NMOSFETs 110, 112, 118, and 128 do not conduct current away from the output node 130. Thus, the current from the current source 132 charges up the output node 130 to a logical high state in that case. For any other logical states of the first and second input signals, A and B, at least one of the first NMOSFET 110 and the fourth NMOSFET 120 conducts current out of the output node 130 to couple the output node 130 to ground such that a logical low state is formed at the output node 130.
In the prior art programmable AND gate 100 of FIG. 1, a constant amount of current from the current source 132 is dissipated when at least one of the first NMOSFET 110 and the fourth NMOSFET 120 conducts current out of the output node 130 to couple the output node 130 to ground. Such constant current flow results in disadvantageous power dissipation. In addition, device dimensions are constantly scaled down with advancement of IC (integrated circuit) technology. However, as supply voltages are further scaled down along with device dimensions, the noise margin of the prior art programmable AND gate 100 of FIG. 1 disadvantageously decreases to deteriorate the performance of the AND gate 100. In addition, the steady state current of the current source 132 does not necessarily scale down with device dimensions such that the prior art programmable AND gate 100 of FIG. 1 still has disadvantageous steady state power dissipation even with scaling down of device dimensions.
Thus, a mechanism is desired for implementing programmable logic devices such as programmable AND gates and programmable OR gates with minimized static power dissipation and with further scalability of device dimensions and supply voltages.